This application claims the benefit of the Korean Application No. P2001-57275 filed on Sep. 17, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a nonvolatile ferroelectronic memory, and more particularly, to a nonvolatile ferroelectric memory, and a method for driving the nonvolatile ferroelectric memory.
2. Discussion of the Related Art
The ferroelectric memory, i.e., FRAM(Ferroelectric Random Access Memory) is paid attention as a next generation memory. In general, the FRAM has a data processing speed similar to that of a DRAM(Dynamic Random Access Memory), and is capable of conserving data even if the power is turned off. Also, the FRAM is similar to the DRAM in structure and includes a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of data even after removal of an electric field.
FIG. 1 illustrates a conventional characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to FIG. 1, in general, a polarization induced by an electric field is not erased totally, but a certain amount (xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) of which is remained, even if the electric field is removed due to existence of the residual polarization(or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states correspond to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 respectively in application to a memory.
FIG. 2 illustrates a unit cell of a conventional non-volatile ferroelectric memory.
Referring to FIG. 2, the unit cell of the conventional non-volatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed in a perpendicular direction to the bitline, a plateline P/L formed in a parallel direction with the wordline W/L, a transistor TI having a gate connected to the wordline W/L and a drain connected to the bitline B/L, and a ferroelectric capacitor FC1 having a first terminal connected to the drain of the transistor T1 and a second terminal connected to the plateline P/L.
The data input/output operation of the conventional nonvolatile ferroelectric memory will be explained. FIG. 3A is a diagram illustrating timing of a write mode operation of the conventional ferroelectric memory, and FIG. 3B is a diagram illustrating timing of a read mode operation of the conventional ferroelectric memory.
In the write mode operation, when an external chip enable signal CSBpad transits from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d and, on the same time, an external write enable signal WEBpad transits from xe2x80x9chighxe2x80x9d to xe2x80x9clow,xe2x80x9d a write mode is started. When address decoding is started in the write mode, a pulse to be applied to the wordline W/L transits from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 to select the unit cell. Thus, in a period during which the wordline W/L is held xe2x80x98highxe2x80x99, the plateline P/L has a xe2x80x98highxe2x80x99 signal applied thereto for one period and a xe2x80x98lowxe2x80x99 signal applied thereto for another period in succession. In order to write a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 on the selected cell, a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 signal synchronized to the write enable signal WEBpad is applied to the bitline B/L. That is, if a xe2x80x98highxe2x80x99 signal is applied to the bitline B/L, and a signal applied to the plateline P/L is xe2x80x98lowxe2x80x99 in a period during which a signal applied to the wordline W/L is in a xe2x80x98highxe2x80x99 state, a logical value xe2x80x981xe2x80x99 is then written on the ferroelectric capacitor FC1. If a xe2x80x98lowxe2x80x99 signal is applied to the bitline B/L, and a signal applied to the plateline P/L is xe2x80x98highxe2x80x99, a logical value xe2x80x980xe2x80x99 is then written on the ferroelectric capacitor FC1.
Next, the read mode operation of reading the data stored in the unit cell will be explained.
If the chip enable signal CSBpad transits from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 externally, all bitlines B/L are equalized to a xe2x80x98lowxe2x80x99 voltage by an equalizer signal before the wordline W/L is selected. Then, after the bitlines B/L are disabled, an address is decoded, and the decoded address transits the wordline W/L from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99, to select the unit cell. A xe2x80x98highxe2x80x99 signal is applied to the plateline P/L of the selected cell, to break a data Qs corresponding to a logical value xe2x80x981xe2x80x99 stored in the ferroelectric memory.
If a logical value xe2x80x980xe2x80x99 is in storage in the ferroelectric memory, a data corresponding to the logical value xe2x80x980xe2x80x99 is not broken. The non-broken data and the broken data thus provide values different from each other according to the aforementioned hysteresis loop, such that a sense amplifier senses a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99.
That is, in the hysteresis loop of FIG. 1, that the data is broken is a case where the value is changed from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99, and that the data is not broken is a case where the value is changed from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case where the data is broken, the logical value xe2x80x981xe2x80x99 is provided as amplified, and in the case where the data is not broken, the logical value xe2x80x980xe2x80x99 is provided as amplified.
After the sense amplifier amplifies data, since an original data should be restored, the plateline P/L is disabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 in a state a xe2x80x98highxe2x80x99 signal is applied to the wordline W/L.
A conventional nonvolatile ferroelectric memory cell array having sub bitlines and main bitlines will be explained.
Though not shown in the drawing, the conventional nonvolatile ferroelectric memory cell array is provided with a plurality of main bitlines crossing sub cell array blocks. The sub cell array block has sub bitline therein in correspondence to the main bitline. There is a switching device SW1, SW2, - - - , or SWn between the sub bitline and the main bitline for electrical connection.
FIG. 4 illustrates one conventional sub cell array block in detail.
Referring to FIG. 4, the sub cell array block has cells arranged in a plurality of rows and columns. Also, there are a plurality of wordline pairs each having a wordline WL and a plateline PL arranged, repeatedly. There are a plurality of main bitlines in a direction crossing the wordline paris WL less than 0 greater than , PL less than 0 greater than , - - - , WL less than 63 greater than , PL less than 63 greater than . The drawing shows an example in which 64 rows are provided. Each cell is arranged at every two columns in a row, and each cell is arranged at every two rows in a column. Therefore, once one of the wordlines and one of the platelines are enabled, only cells connected either to odd numbered sub bitline, or even numbered sub bitline are selected. Such a cell array is called as a folded bitline cell array, in which no cells overlap when the cell array is folded centered on the main bitline, when a unit cell is provided among the wordline WL, the plateline PL, and the sub bitline, and the switching device SW1, or SW2, - - - is provided at an end of the sub bitline for controlling connection between the sub bitline and the main bitline. The unit cell includes one transistor and one ferroelectric capacitor, wherein the transistor has a gate connected to a wordline, and the ferroelectric capacitor has one terminal connected to a drain (or source) of the transistor, and the other terminal connected to a plateline.
Structures of the ferroelectric capacitor, the sub bitline, and the main bitline in the foregoing nonvolatile ferroelectric memory cell array will be explained, briefly.
FIG. 5 illustrates a section of a structure of the unit cell in FIG. 4.
Referring to FIG. 5, the unit nonvolatile ferroelectric memory cell includes a gate electrode 252 in one region of a silicon substrate 251, a source 253a and a drain 253b in the silicon substrate 251 on both sides of the gate electrode 252, a sub bitline 258 in one direction brought into contact through the drain 253b, a contact plug 256, and a contact pad 257. The numerals 254 and 255 denote first and second interlayer insulating films, respectively. There is a third interlayer insulating film 259 deposited on the sub bitline 258, and a capacitor contact plug 260 in a contact hole formed through the first to third interlayer insulating films 254, 255, and 259 and the sub bitline 258 to expose the source 253a. There is a fixed pattern of a stack of a lower electrode 261 of the capacitor, a ferroelectric film 262, and an upper electrode 263 of the capacitor in contact with the capacitor contact plug 260. There is a main bitline 269 isolated from the ferroelectric capacitor designed to be connected to the sub bitline under the control of the switching device (not shown in the drawing) over the ferroelectric capacitor. Thus, the sub bitline is arranged below the ferroelectric capacitor and the main bitline is arranged over the ferroelectric capacitor.
The foregoing related art nonvolatile ferroelectric memory cell array has the following problems.
There is a limitation in a stable operation of the cell with the ferroelectric capacitor at a low voltage.
Moreover, because both the writing of a logical value xe2x80x9c1xe2x80x9d and a logical value xe2x80x9c0xe2x80x9d are carried out in the pre-charge time period, there is a limitation in reducing the pre-charge time period.
Accordingly, the present invention is directed to a nonvolatile ferroelectric memory, and a method for driving the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile ferroelectric memory which can improve a chip operation speed.
Another object of the present invention is to provide a ferroelectric memory applicable to a chip which is operable even at a low voltage.
A further object of the present invention is to provide a method for driving a nonvolatile ferroelectric memory, which can reduce a pre-charge time period.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory includes a top cell array block and a bottom cell array block, each array block having sub cell array blocks, each sub cell array block having a plurality of unit cells; a plurality of main bitlines arranged in one direction in correspondence to a column unit of the sub cell array blocks; a plurality of sub bitlines each connected to one terminal of one of the plurality of unit cells arranged in a same direction as the one direction of the main bitlines; a sense amplifier block having sense amplifiers between the top cell array block and the bottom cell array block, each sense amplifier for amplifying a signal from the main bitline; sub bitline first switch signal application lines and sub bitline second switch signal application lines for controlling connection of the sub bitlines and the main bitlines, sub bitline pull up signal application lines for controlling pull up of the sub bitlines by a self boost operation, and sub bitline pull down signal application lines for selective pull down of the sub bitlines, which are arranged perpendicular to the sub bitlines in correspondence to the sub cell array blocks; a first switch device in each sub cell array block in correspondence to a column direction for operation under control of the sub bitline first switch signal application line; a second switch device in each sub cell array block in correspondence to a column direction for selective transfer of a signal from the sub bitline pull up signal application line to the sub bitline under the control of the sub line second switch signal application line; and, a third switch device in each sub cell array block in correspondence to a column direction for selective pull down of the sub bitline under control of the sub bitline pull down application line.
In another aspect of the present invention, there is provided a method for driving a nonvolatile ferroelectric memory, in which a sub bitline is enabled, and pulled up/pulled down by a self boost operation, the sub bitline being selected by a sub bitline first switching signal application line, a sub bitline second switching signal application line, a sub bitline pull up signal application line, and a sub bitline pull down signal application line, and when a continuous active period is divided into t1, t2, t3, t4, and t5 sections, and a pre-charge period is divided into t0, and t6 sections, the method comprising the steps of: (a) applying a first high level voltage to the sub bitline pull down signal application line in the t0 section, for pulling down a sub bitline and a main bitline to a low level; (b) applying a low level voltage to the sub bitline pull down signal application line in the t1 section; (c) applying a second high level voltage higher than the first high level voltage to a wordline in the t2, t3, and t4 sections, and to a plateline in the t2, and t3 sections, and applying the first high level voltage to the sub bitline first switch signal application line in the t2, and t3 sections, for transferring cell data to the sense amplifier through the sub bitline and the main bitline; (d) applying the second high level voltage to the sub bitline second switch signal application line, and transiting the plateline to the low level, both in the t4 section, and applying the second high level voltage to the sub bitline second switch signal application line in the t5 section, for self boosting the sub bitline second switch signal application line and the word line to a third high level voltage higher than the second high level voltage, thereby writing logic xe2x80x9c1xe2x80x9d data on a ferroelectric capacitor; and, (e) transiting the wordline and the plateline to the second high level, and applying the first high level voltage to the sub bitline first switch application line, both in the t6 section, for writing logic xe2x80x9c0xe2x80x9d data in the ferroelectric capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.